Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a storage capacitor that stores the data in the cell and an access transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit and is usually either a high voltage, logic 1, or a low voltage, logic 0.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. However, each such memory cell is coupled to, or associated with, only one digit line of the digit line pair through an access transistor.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the selected word line activates the access transistors for a given word line address, the charge of the selected memory cells are shared with their associated digit lines, and data is sensed and latched to the digit line pairs.
Memory arrays are often divided into subarrays having a number of rows of memory cells. The rows may be grouped into local phases, facilitating access to a specific group of rows in the subarray. Local phases from multiple subarrays may further be grouped into global phases, facilitating access to a specific group of local phases in the array. Global phase drivers enable the groupings of local phases. Local phase drivers, in turn, enable the groupings of rows in the subarrays. Word line drivers enable individual rows. In normal operation, only one local phase may be enabled in each subarray, and back-to-back activate row commands are not permissible within a single subarray.
Memory devices having memory arrays are usually tested to verify reliability. A variety of testing procedures are utilized and usually include tests that stress the memory device beyond its design parameters. It is expected that a device passing a stress test will operate correctly under normal use conditions. Memory devices often have logic and circuitry to facilitate testing, and such logic and circuitry are generally responsive to one or more external signals to signify that a test mode should be entered and a test performed.
The ability to sense the data stored in the storage capacitor is a critical operation of the memory device. A memory device operating near the capabilities of the sensing operation may fail in use. Accordingly, there is a need in the art for testing procedures capable of stressing the sensing operation of memory devices, and logic and circuitry to facilitate such testing.